Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors and are often accordingly referred to by the number of transistors, for example, six-transistor (6-T) SRAM, eight-transistor (8-T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a bit into, or read a bit from, the SRAM cell.
With the increasing down-scaling of integrated circuits, the power supply voltages of the integrated circuits are reduced, along with the power supply voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which are used to indicate how reliably the bits of the SRAM cells can be read from and written into, are reduced. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations.
Various approaches have been explored to lower VCCmin, which is the minimum power supply voltage VCC required for reliable read and write operations, and to suit the ever-decreasing power supply voltages. For example, a negative bit-line technique was used to improve cell write-ability at low power supply voltages, particularly when the word-line voltage is suppressed. Referring to FIG. 1, which is a 6-T SRAM cell connected to negative-voltage generator 120. Assuming a “0” bit is to be written into illustrated SRAM cell 100, bit-line BL hence carries a low voltage representing a logic low, and bit-line BLB carriers a high voltage representing a logic high. Before the write operation, node 110 is at a high voltage, while node 112 is at a low voltage. To write a “0” bit into the SRAM cell, a negative voltage, for example, −100 mV, is put on bit-line BL. The negative voltage causes an increase in the voltage difference between node 110 and bit-line BL. Accordingly, the write operation becomes easier, and VCCmin is reduced.
The negative bit-line technique, however, comes with a price. As shown in FIG. 2, the negative voltage as illustrated is generated using negative-voltage generator 120, as shown in FIG. 1, which includes a charge pump receiving power supply voltage VDD and generating the negative voltage. FIG. 2 schematically illustrates the relationship between power supply voltage VDD and the negative bit-line voltage generated by negative-voltage generator 120. It is noted that if power supply voltage VDD becomes lower, the magnitude of the negative voltage also reduces. This trend, however, defeats the purpose of having the negative bit-line voltage. As is well perceived, if power supply voltage VDD is reduced, the magnitude of the negative bit-line voltage needs to be greater in order to offset the reduction in power supply voltage VDD. To generate a lower negative voltage, the capacitor in negative-voltage generator 120 needs to be larger, and hence requires a greater chip area. A new negative-voltage generator is thus needed to solve the above-discussed problem.